Suma.J, Mahesh B Neelagar, Shwetha N, & Niranjan L. (2022). Simulation and Synthesis of Efficient Majority Logic Fault Detector Using EG-LDPC Codes to Reduce Access Time for Memory Applications. International Journal of Engineering and Management Research, 12(6), 224–233. https://doi.org/10.31033/ijemr.12.6.31