SUMA.J; MAHESH B NEELAGAR; SHWETHA N; NIRANJAN L. Simulation and Synthesis of Efficient Majority Logic Fault Detector Using EG-LDPC Codes to Reduce Access Time for Memory Applications. International Journal of Engineering and Management Research, [S. l.], v. 12, n. 6, p. 224–233, 2022. DOI: 10.31033/ijemr.12.6.31. Disponível em: https://ijemr.vandanapublications.com/index.php/ijemr/article/view/1066. Acesso em: 15 may. 2024.